1. Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog .
2. Responsibilities include ASIC/SoC IP integration , linting, synthesis, and working closely with verification teams.
3. Requires solid fundamentals in digital design , timing closure, and understanding of the ASIC flow.
4. You'll debug simulation failures, implement ECOs, and support gate-level simulations.
5. Collaborate with cross-functional teams (SW, DV, Physical Design) to achieve tapeout goals.
6. Bachelor's or Master's degree in engineering in EE/CS is essential, along with 2-3 years of relevant experience.
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📌 RTL Design Engineer (Hyderabad)
🏢 ACL Digital
📍 Hyderabad
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