Job Description RTL Design Engineer
n Key Responsibilities
n n Analyze architectural specifications and define detailed microarchitecture for digital design blocks.
n Develop synthesizable RTL using Verilog/SystemVerilog for IPs, subsystems, and SoC components.
n Create and maintain design documentation, including microarchitecture specifications, interface definitions, and implementation guidelines.
n Collaborate with architecture teams to evaluate design trade-offs and optimize solutions for performance, power, and area (PPA).
n Perform RTL quality checks, including:
n Lint analysis
n CDC (Clock Domain Crossing) checks
n RDC (Reset Domain Crossing) checks
n Synthesis and design rule compliance reviews
n Support functional verification teams by reviewing test plans, debugging simulation failures, and resolving design issues.
n Work closely with RTL integration teams to ensure proper subsystem and SoC-level integration.
n Support synthesis, timing analysis, and physical design teams in achieving timing and implementation closure.
n Analyze and debug functional, timing, and silicon-related issues during pre-silicon and post-silicon phases.




n Participate in design reviews and ensure compliance with coding standards and development methodologies.
n Contribute to low-power design implementation and power optimization techniques.
n Develop reusable design methodologies, scripts, and automation to improve productivity and design quality.
n Support tapeout activities and provide engineering support through silicon bring-up and validation.
n n Required Skills & Experience
n n Strong experience in RTL design using Verilog/SystemVerilog.
n Solid understanding of digital design fundamentals, computer architecture, and SoC design concepts.
n Experience in microarchitecture development and RTL implementation.
n Knowledge of AMBA protocols (AXI, AHB, APB) and standard on-chip interconnects.
n Familiarity with lint, CDC, RDC, synthesis, and static timing analysis flows.
n Understanding of low-power design techniques, clock gating, reset architecture, and power intent methodologies.
n Experience with EDA tools for simulation, synthesis, and RTL quality analysis.
n Strong debugging and problem-solving skills.
n Ability to work effectively in cross-functional teams and manage multiple tasks in a rapid-paced development environment.
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📌 rtl design engineer (Bengaluru)
🏢 Mirafra Technologies
📍 Bengaluru