Dfx/dft Verification Engineer Uvm Systemverilog Ijtag Bengaluru (India)

Dfx/dft Verification Engineer Uvm Systemverilog Ijtag Bengaluru (India)

03 Aug
|
Spatial Alphabet
|
India

03 Aug

Spatial Alphabet

India

Job Title: DFX/DFT Verification Engineer | UVM | SystemVerilog | IJTAG

Experience: 7–10 Years

Job Summary

We are seeking an experienced DFX/DFT Verification Engineer with robust expertise in Design for Test (DFT) verification methodologies. The ideal candidate should have hands-on experience in DFT logic verification, UVM-based verification environments, and SystemVerilog, along with knowledge of IJTAG, ICL, and PDL standards.The selected candidate will work closely with Design, DFT, and Verification teams to ensure robust testability and high-quality silicon for complex ASIC and SoC designs.

Key Responsibilities

· Develop and execute verification plans for DFT/DFX features.

· Perform DFT logic verification using SystemVerilog and UVM.

· Develop reusable UVM-based verification environments and test benches.

· Create directed and constrained-random test cases for DFT validation.

· Verify scan, boundary scan, IJTAG, and other DFT functionalities.

· Debug RTL and test bench failures and perform root-cause analysis.

· Collaborate with Design and DFT teams to resolve functional and verification issues.

· Automate verification and regression flows using scripting where required.





· Ensure complete verification coverage and support successful silicon bring-up.

Required Skills

· 7–9 years of experience in ASIC/SoC Design Verification.

· Robust experience in DFT/DFX Logic Verification.

· Excellent knowledge of SystemVerilog (SV).

· Strong hands-on experience with UVM (Universal Verification Methodology).

· Experience with IJTAG (IEEE 1687).

· Good understanding of ICL (Instrument Connectivity Language).

· Experience with PDL (Procedural Description Language).

· Strong debugging and verification skills.

· Positive understanding of ASIC/SoC verification methodologies.

Preferred Skills

· Experience with scan architecture and DFT implementation concepts.

· Knowledge of regression automation.

· Familiarity with EDA simulation and debug tools (VCS, Verdi, etc.).

· Strong analytical and problem-solving abilities.

· Good communication and teamwork skills.

Education

· B.E./B.Tech/M.E./M.Tech in Electrical Engineering, Electronics & Communication, VLSI, or a related discipline.

Pay: ₹1,500,000.00 - ₹2,000,000.00 per year

Work Location: In person

📌 Dfx/dft Verification Engineer Uvm Systemverilog Ijtag Bengaluru (India)
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