We are seeking an experienced RTL Verification Engineer with expertise in functional verification of complex digital designs using System Verilog and UVM methodologies. The candidate will be responsible for developing verification environments, executing comprehensive verification plans, and ensuring high-quality product delivery.
Key Responsibilities
Understand design specifications and develop verification strategies and plans.
Develop UVM/System Verilog-based verification environments.
Create testcases, scoreboards, monitors, assertions, and coverage models.
Perform block-level, subsystem-level, and SoC-level verification.
Drive functional, code, assertion, and toggle coverage closure.
Execute regressions and analyze simulation results.
Debug RTL and verification workplace issues in collaboration with design teams.
Participate in reviews and verification sign-off activities.
Required Skills
Robust expertise in System Verilog and UVM.
Experience in functional verification of ASIC/FPGA designs.
Strong understanding of verification methodologies and coverage-driven verification.
Hands-on experience with assertions (SVA), regression management, and debugging tools.
Knowledge of digital design concepts and RTL architecture.
Protocol Experience (One or More)
PCIe
Ethernet (1G/10G/25G/100G)
AXI/AHB/APB
DDR/LPDDR
NVMe
USB
I2C/SPI/UART
MIPI
Preferred Qualifications
Experience with formal verification and low-power verification.
Knowledge of SoC/IP verification methodologies.
Exposure to emulation or FPGA-based validation is desirable.
Knowledge of ISO 26262 Functional Safety, safety verification, and safety mechanisms is a solid advantage.
Experience in requirements traceability and compliance-driven development is a plus.
Education
B.E./B.Tech/M.E./M.Tech in Electronics, VLSI, Electrical Engineering, Computer Engineering, or related disciplines.