Role Summary: Responsible for micro‑architecture definition and RTL design of high‑quality IPs, driving digital design from specification to sign‑off.
Key Responsibilities:
Develop micro‑architecture specs and design documentation
Design and deliver RTL (Verilog/VHDL/System Verilog)
Execute Lint, CDC, Synthesis, and DFT flows
Participate in RTL reviews and support verification/debug
Drive IP quality and sign‑off readiness
Required Skills:
Solid digital IC design experience in semiconductor industry
Expertise in RTL design and design flows
Knowledge of protocols (Ethernet, CAN, SPI) and buses (AMBA/AXI)
Experience with ARM/TriCore CPUs
Familiarity with ISO 26262 functional safety
Valuable communication and cross‑functional collaboration skills
Tools:
SpyGlass Lint, CDC tools, Cadence/Synopsys Synthesis, Tessent DFT, Mentor/Cadence simulators
Pay: Up to ₹3,000,000.00 per year
Work Location: In person
📌 Rtl Design Engineer Chennai
🏢 Nanocore System
📍 Chennai
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