Your key responsibilities will include but not be limited to:
Perform end-to-end analog/mixed-signal verification of RFICs from block-level through full-chip integration, leveraging schematic, behavioral, and functional views to achieve comprehensive coverage while meeting project schedules.
Develop Verilog-A and SystemVerilog RNM behavioral models for analog and mixed-signal circuits. Perform equivalence checks to validate behavioral models match schematics.
Define and execute verification plans derived directly from product specifications.
Partner closely with design teams to develop deep understanding of custom circuits, providing verification feedback on functionality and performance.
Review layout and floorplans to proactively identify and resolve issues.
Continuously improve verification methodologies with an emphasis on scalability, reusability, and portability across programs.
Optimize models to ensure accuracy while maintaining productive simulation performance
Document modeling and verification methodologies, and promote best practices across teams and programs.
Stay current with industry trends and emerging techniques in analog and mixed-signal modeling and verification.