At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The person should be an Electrical, Electronics or Computer Science Engineer with very valuable understanding of HDLs (Verilog and/ or VHDL).
Prior experience in simulation/emulation using these languages. He/ she should have a positive working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools.
Experience in process automation with scripting.
Experience with SystemVerilog, C++, UVM.
Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog.
Experience designing and implementing complex functional verification settings is required.
Knowledge of protocols like PCIe, USB3/4, DP an added advantage.
We’re doing work that matters. Help us solve what others can’t.
📌 Sr Principal Product Validation Engineer Noida
🏢 Cadence Design Systems
📍 Noida
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