- Block Level and Full chip level Static(IR)/Energetic(IVD) sign-off
- Signal/Power EM sign-off at Block level and Full chip
- Custom power grid implementation for block/hardmacs
- System level Analysis (PDN) with board, package, interposer and die
- Work with SoC and packaging team in bump assignment, pkg routing optimization
- Dynamic analysis with vectorless/vectors/mixed mode analysis
- PG Grid resistance checks
- Knowledge of physical implementation is a plus
Skill Set :
- Hands-ons experience in RedHawk/RHSC/Voltus/PDN analysis/3DIC
- Good understanding on Power Integrity Signoff Checks
- Knowledge of Perl, TCL, Python
- Familiarity with Innovus/ICC
- Ability to communicate effectively with global cross functional teams
📌 IC Design Engineer 4 (Bengaluru)
🏢 VMware
📍 Bengaluru
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