Job Requirements

- Bachelor's degree with 12 years of experience or a Master's degree with over 10 years of experience.

- Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules).

- Strong layout knowledge in submicron processes (e.g., 7nm, 5nm, 3nm, 2nm).

Key Responsibilities

- Understand and apply layout guidelines, current process rules, and technical requirements for high-quality layouts.

- Manage scheduling, timelines, and layout floor-planning.

- Ensure end-to-end deliverables are completed with high quality and within the planned schedule.

- Adapt quickly to new methodologies and communicate effectively with the SOC and library teams.

Skill Set(Memory)

- Strong experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration).





- Experience with Cadence Layout tools (Virtuoso XL, VXL, or EXL) and Calibre verification tools.

- Proficiency in floor-planning, hierarchy layout, and chip integration.

- Solid understanding of memory architecture and RC requirements, with the ability to plan signal and power routing.

- Ability to lead teams, train junior engineers, and manage projects effectively.

- Strong knowledge of memory layout topology;

experience with memory compilers is preferred.

- Knowledge of AI, layout automation, and script/SKILL programming is preferred.

- Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.

- Self-reliant with the ability to work both independently and collaboratively.

R026710

📌 Sr. Memory Layout Design Engineer (Bengaluru)
🏢 Broadcom
📍 Bengaluru