Experience : 7.00 + years
Salary : INR 5000000-7500000 / year (based on experience)
Expected Notice Period : 30 Days
Shift : (GMT+05:30) Asia/Kolkata (IST)
Opportunity Type : Remote
Placement Type : Full Time Permanent position(Payroll and Compliance to be managed by: Architect Labs)
**(*Note: This is a requirement for one of Uplers' client - Architect Labs)
**What do you need for this opportunity?
Must have skills required: tapeout, design verification, protocol, SOC, Subsystem debugging, SystemVerilog, UVM
Architect Labs is Looking for:**** As a Founding Member of the Technical Staff (Design Verification) at Architect Labs, you''''ll own verification strategy for AI-generated designs taping out on leading foundries, working at the intersection of hardware verification and AI-driven design automation.
- Review AI-driven test plans and validation strategies for internal/external SoC projects.
- Provide domain expertise to AI/ML teams (architectural & microarchitectural checks, validation modularity, checkers, coverage models, interface protocols), encoding DV best practices into AI flows.
- Define, drive, and coordinate validation, verification, and integration across multiple IPs, including checkpoints and handoffs.
- Collaborate with architecture, design, and AI/ML leads to generate simulation- and emulation-ready collateral at scale.
- Track trends in semiconductor verification and AI-driven design automation to keep methodology cutting-edge.
- What We''''d Like to See
Qualifications & Skills:
- Degree: Bachelor’s/Master’s/PhD in Electrical/Computer Engineering or related field.
- Tapeout Experience: 5+ years (10+ preferred) on advanced-node tapeouts end-to-end silicon delivery is a strong plus.
- Verification Expertise: Deep experience in verification/validation, emulation, and system-level verification of standard IPs strong track record with microarchitectural checkers/monitors, SoC validation platforms, and reusable collateral.
- Coding: Solid SystemVerilog, UVM, C/C++ Python preferred.
- Subsystem Depth: Hands-on in at least one: ARM/AMBA (APB, AHB, AXI, ideally ACE) / CPU subsystems (boot, interrupts, debug, coherency) / Memory controllers/PHY (LPDDR/DDR) / Interconnect/NoC (routing, arbitration, QoS, bandwidth) / NPU/ML accelerators (datapath, scratchpad, DMA) / Security IP / secure enclaves
- Methodology: Experience with simulation/emulation flows FPGA prototyping for fast functional verification.
- Execution: Strong problem-solving, collaboration, communication, attention to detail ability to work independently and align cross-functionally.
- Leadership: Ability and intent to lead DV as the team scales.
Bonus:
- SoC-level DV (full system bring-up: memory controller + PHY + CPU connectivity, top-level integration).
- Deep AMBA expertise, especially ACE.
- FPGA prototyping (Xilinx Vivado/Vitis preferred).
- Broad DV across interconnects, CPU subsystems, AMBA, memory controllers, NPUs.
- Tapeout experience at frontier AI chip startups (MatX, Groq, Cerebras, d-Matrix) or tier-1 companies (Apple, NVIDIA, Google, Qualcomm, Broadcom, AMD).
Interview Process:
- Technical R1 (Code writing)
- Technical R2 (Technical discussions + Live Coding + Behavioural)
How to apply for this opportunity?
- Step 1: Click On Apply! And Register or Login on our portal.
- Step 2: Complete the Screening Form & Upload updated Resume
- Step 3: Increase your chances to get shortlisted & meet the client for the Interview!
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📌 Member of Technical Staff - Design Verification (India)
🏢 Uplers
📍 India