Job Title: Senior / Lead FPGA Design & Validation Engineer

Location: India (Hybrid / Onsite)

Experience Level: 4.5 – 14 Years

Notice Period: Immediate Joiners to 15 Days Max About the Role

We are seeking highly skilled and hands-on FPGA Design & Validation Engineers (ranging from Mid-Level to Lead) to join our high-performance Silicon & FPGA Engineering team. In this role, you will be responsible for the end-to-end architecture, RTL implementation, silicon-level validation, and deep hardware debugging of complex FPGA systems and IPs.

If you thrive in dynamic environments solving complex board-level, timing, and protocol challenges using advanced FPGA architectures and state-of-the-art lab/debug setups, this opportunity is for you. Key Responsibilities

FPGA Architecture & RTL Design: Design, develop, and integrate complex IP modules and subsystems using Verilog / SystemVerilog / VHDL.

Pre-Silicon Verification & Testing: Build reusable testbenches, write targeted test cases, and perform functional verification to validate design intent prior to hardware bring-up.

Post-Silicon Hardware Validation: Drive hands-on bring-up, post-silicon validation, and lab testing of FPGA-based boards and silicon prototypes.

Deep Hardware Debugging: Diagnose and resolve complex timing closure issues, physical layer protocol failures, clock domain crossing (CDC) bugs, and board-level hardware glitches using logic analyzers, oscilloscopes, and embedded logic analyzers (e.g., ChipScope, SignalTap, Identify).

Protocol & Interface Integration: Implement and debug high-speed serial/parallel interfaces and standard protocols (e.g., PCIe, AMBA AXI/AHB/APB, Ethernet, SPI, I2C, DDR3/DDR4).





Cross-Functional Collaboration: Work closely with cross-functional teams including Board Design, Embedded Firmware, Systems Architecture, and Software to ensure seamless FW-HW integration and tape-out readiness.

Required Technical

Skills & Experience

Experience: 4.5 to 14 Years in FPGA RTL Design, Emulation, and Post-Silicon Hardware Validation.

RTL Development: Strong command over SystemVerilog, Verilog, or VHDL for high-density FPGA architectures.

FPGA Design Tools: Hands-on experience with major industry-standard FPGA toolchains (e.g., Libero SoC, Vivado, Quartus) for synthesis, place & route, and timing closure.

On-Chip & Lab Debugging: Exceptional debugging skills using embedded logic analyzers (In-system probes) as well as lab equipment (Oscilloscopes, Logic Analyzers, Protocol Analyzers).

Protocols: Solid expertise with protocols like AMBA (AXI/AHB/APB), PCIe, Ethernet, SPI/I2C, or memory controllers (DDR/SRAM).

Timing & CDC: Solid grasp of Static Timing Analysis (STA), constraint creation (SDC), constraint debugging, and handling multi-clock domain designs.

Preferred / Plus Skills

Exposure to SoC FPGA architectures, embedded processors (RISC-V, ARM), and FW-HW co-verification.

Experience with low-power FPGA architectures, security primitives, or motor control/industrial automation IPs.

Proficiency in scripting languages (TCL, Python, or Perl) to automate build, synthesis, and validation flows.

Candidate Availability

Requirement

⚠️ Strict Notice Period Constraint: Candidates must be Immediate Joiners or currently serving a notice period with a maximum availability of 15 days. Candidates with longer notice periods will not be considered.

📌 FPGA (Hyderabad)
🏢 ACL Digital
📍 Hyderabad