: Senior Formal Verification Engineer Seeking an experienced Senior Formal Verification Engineer to drive end‑to‑end formal verification of complex IP/Sub-system SoC designs. The engineer should operate independently, contribute deep technical expertise, and deliver high‑quality signoff packages in a fast‑paced setting. Location - Bangalore

Notice Period - Immediate to 30 Days Key Responsibilities:

- Develop and execute formal verification plans for IP‑level and subsystem designs.

Write high‑quality SVA/PSL properties and build complete formal environments.

Perform property proofs, coverage closure, abstraction modeling, and over/under‑constraint analysis.

Debug counterexamples and root‑cause design issues.

Provide regular reports, documentation, and formal sign-off deliveries.

Collaborate with Verification lead, RTL designers, and simulation teams to ensure design correctness.

Required Skills & Experience:

- 6-20 years of hands‑on experience in Formal Property Verification (FPV).





Strong proficiency in SystemVerilog Assertions (SVA) and formal tools (Jasper Gold, or any other equivalent formal tool).

Solid understanding of RTL design, microarchitecture, FSMs, clock/power domains, and interface protocols (AMBA AXI/APB/AHB).

Demonstrated experience with abstraction, COI analysis, vacuity checks, and formal completeness metrics.

Excellent debugging and analytical problem‑solving skills.

Preferred

Skills

- Experience with multilayer buses/ bus interconnects.

Knowledge of scripting languages (Python, Perl, TCL).

Engagement

Expectations

- Work independently with minimal supervision.

Provide weekly status updates and maintain reproducible formal environments.

Deliver complete formal signoff packages as per project timelines.

Adhere to all confidentiality, documentation, and security protocols. Working from office.

📌 Formal Verification Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru