KEY RESPONSIBLITIES: Drive full chip IR/EM convergence on multiple ASICs across different technology nodes. Work closely with architecture, power management, package and floorplan team to come up with robust power delivery design. Work with RTL and PD team in coming up with the low power and UPF specification for the SoC. Work closely with CAD team to come up with current flows and methodologies in the power integrity domain.
PREFERRED SKILLSET: 3+ years of professional experience in the industry with a proven track record of successfully delivering complex SoCs Sound knowledge of Power delivery and power integrity domains Hands on experience on industry standard tools especially Redhawk based power integrity analysis Should have lead IR/EM convergence on full chip SoCs Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker
ACADEMIC CREDENTIALS:* Bachelors or Masters degree in Electronics/Electrical Engineering