Hiring for DFT Engineers

Location - Bangalore

Experience - 5 to 15yrs

NOTE: Immediate candidates are preferred.

Key Responsibilities

● Execute and support Design-for-Test (DFT) activities including scan insertion, ATPG, and

OCC integration

● Perform DRC debug, test coverage analysis, and simulation debug across various stages of the DFT flow

● Analyze and resolve issues related to testability, fault coverage, and pattern generation

● Work with advanced DFT methodologies including SSN, IJTAG, ICL, and PDL handling

● Collaborate with cross-functional teams to ensure smooth DFT integration and issue resolution

● Contribute to continuous improvement of DFT flows, methodologies, and debug efficiency

Required Skills & Experience

● Robust understanding of DFT fundamentals including ATPG, scan architecture, and OCC

● Proven hands-on experience in:

● DRC debug, Coverage debug,Simulation debug (various modes and scenarios)

● Exposure to SSN, IJTAG, ICL, and PDL frameworks

● Synopsys Memory Bist, Tetramax, SMS

● Ability to analyze complex issues and provide structured debug solutions

📌 DFT Engineers (Bangalore Metropolitan Area)
🏢 smartsoc solutions
📍 Bangalore Metropolitan Area