At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

- This role requires close interaction with multiple cross functional teams across geographies to align on project receivables/deliverables.
- Mentoring junior engineers and driving innovation/automation.
- BE/B.Tech/M.E/M.Tech with 7+ years of relevant work experience and strong understanding of DFT concepts and good communication skills.
- Strong hands-on experience using industry standard EDA Tools.
- Experience with logic simulators from one or more EDA vendors.
- Experience on industry standard ATPG tools like Cadence Modus.
- Experience with RTL lint tools like Jasper.
- Experience in scan insertion, coverage analysis and debugging skills on faults coverage enhancement is required.




- Programming in Perl/Tcl/Python or other scripting languages is a plus.
- Experience in post silicon validation, ATE debug and support is desired.
- Exposure to RTL2GDS flow and tasks such as synthesis and scan insertion, STA and IR drop.
- Positive understanding of Logic design, RTL implementation & verification, logic synthesis, Logic Equivalent Checking & Static Timing Analysis are plus.
- Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability.

We’re doing work that matters. Help us solve what others can’t.

📌 Principal DFT Design Engineer (India)
🏢 Cadence Design Systems
📍 India