- Good expertise in Storage domain NVMe SSD, PCIe.
- Expertise in SystemVerilog, Verification Methodologies such as OVM, UVM,etc.
- Should have worked on at least one full-chip or module-level verification using HVLs. Experience in developing verification plans, Verification environments, Components/BFMs and running simulations at RTL and gate level.
- Knowledge of C/C++ would be an added advantage.
- Possess excellent debugging and problem solving skills.
- Excellent written and verbal communication skills.
- Should be willing to work as an Individual contributor or team setting.
📌 Senior Verification Engineer (India)
🏢 ATRIA LOGIC
📍 India
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