- Experience in complete PNR from the floorplan, Placement, post-placement timing closure, clock tree synthesis, Routing, Post route timing fixing, DRC fixing, PI fixing (IR violation), and closing all required matrices in ECO.
- Valuable knowledge of TCL, shell, and PERL scripting.
- Experience in APR (PNR) and ECO using ICC2 (Synopsys) & INNOVUS (cadence) Tools.
- Experience in working in 4nm,5 nm, 7nm, 10nm, and 16nm technology.
- Experience in doing floorplan with complex design and a large number of macros.
- Flow setup of synthesis, which includes the Timing constraints and logical, physical constraints.
📌 Physical Design Engineer (India)
🏢 DPI
📍 India
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