- Responsible for Functional/Netlist Verification of complex ASIC/SoCs
- Create a Testplan and Coverage plan
- Develop Test bench including TB Components, functional coverage model, setting and Testcases and verify the functionality at for Block and Chip level
Job Requirements:
- 3-8 Years of Experience in ASIC/SoC Design Verification
- Exposure to EDA tools viz. VCS, NC-Sim, Questasim
- Good in debugging and problem solving skills
- Proficient in System Verilog, SVA and C++ and PERL scripting
- Proficient in using verification methodologies like VMM, OVM and UVM
- BE/BTECH/ME/MTECH in EC/EE/CS or related field
📌 Senior/Lead Verification Engineers: (India)
🏢 intsemi
📍 India
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