DFT-Design For Testability (India)

DFT-Design For Testability (India)

05 Aug
|
Jemysto Tech
|
India

05 Aug

Jemysto Tech

India

- 5-7 YearsProject in in 16nm or below, Mixed signal IC.
- Synopsys TestMAX experience
- Stuck-at ATPG
- Transition fault and path-delay ATPG
- Tester failure debug experience
- Excellent in scripting

Nice-to-have:

- ATPG flow development
- RTL DFT analysis
- PrimeTime DFT scripting for at-speed patterns
- SPF porting for analog-on-top design
- BIST pattern development using Synopsys tools"

📌 DFT-Design For Testability (India)
🏢 Jemysto Tech
📍 India

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