Project Role : Functional Verification Engineer
Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.
Must have skills : SoC Verification
Good to have skills : NA
Minimum 5 year(s) of experience is required
Educational Qualification : 15 years full time education

Summary:
As a Functional Verification Engineer, a typical day involves developing and implementing comprehensive testbenches to ensure the functional accuracy of digital designs at both block and system levels. The role includes creating various types of tests, such as constrained-random, directed, and coverage-driven, to thoroughly validate the design. Collaboration with design and architecture teams is a key part of the day, focusing on identifying edge cases and ensuring that all functional aspects are covered before the final design stage. This position requires a proactive approach to problem-solving and continuous communication across teams to maintain high-quality verification standards.

Roles & Responsibilities:

- Expected to be an SME, collaborate and manage the team to perform.




- Responsible for team decisions.
- Engage with multiple teams and contribute on key decisions.
- Provide solutions to problems for their immediate team and across multiple teams.
- Lead efforts to improve verification methodologies and processes to enhance efficiency and coverage.
- Mentor junior team members by providing guidance and support to foster their qualified growth.
- Coordinate with cross-functional teams to align verification goals with overall project timelines and deliverables.

Professional & Technical Skills:

- Must To Have Skills: Proficiency in SoC Verification.
- Experience in developing and executing testbenches using SystemVerilog and Universal Verification Methodology.
- Strong understanding of constrained-random and directed test creation along with coverage-driven verification techniques.
- Ability to collaborate effectively with design and architecture teams to identify and address corner cases.
- Familiarity with debugging and analyzing simulation results to ensure design correctness.
- Knowledge of verification planning and coverage closure strategies.

Additional Information:

- The candidate should have minimum 5 years of experience in SoC Verification.
- This position is based at our Bengaluru office.
- A 15 years full time education is required.

15 years full time education

📌 Functional Verification Engineer (India)
🏢 Accenture
📍 India