- Responsible for design verification at chip level ensuring design meets architectural / system requirements.
- Responsible for developing test workplace, test bench development, bus protocol checking, transaction level checking and performance modeling.
- Experience in advanced verification languages such as VERA, Specman & System C is desrirable.
- 3-5 years of solid design verification experience required.
- Min Educational Requirements BS in EE. MS in EE preferred.
- Email your resume to [email protected] with Job Code – VE in the subject line.
📌 ASIC Design Verification (India)
🏢 Perfectus Technology
📍 India
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