05 Aug
|
Recognized
|
Hyderabad
05 Aug
Recognized
Hyderabad
1. 1. VLSI Front-end
Mid Level Team Leads
Experience: Above
5 Years
Must
have: Experience in RTL/ Verification/ Synthesis/ DFT/
Gatesim; knowledge of Verilog, System Verilog and C/C++;
Must
have led full-fledged reusable, silicon proven IP development effort;
Worked
on USB 3, PCI Express, SATA, EMAC, WI-FI, DDR, and MIPI protocols;
Capacity
to assimilate protocols thoroughly and capability to take them to compliance;
Familiarity
with AMBA bus structure and must have developed some of the bus components.
Engineers
who lead development of verification workplace for any IP using system
verilog and have a flair for venturing into other front-end areas are welcome.
📌 VLSI Front-End (Hyderabad)
🏢 Recognized
📍 Hyderabad