Responsibilities will include, but are not limited to: Design and maintain standard cells layout for new DRAM products on new technology Perform layout verification like LVS/DRC/Latchup, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Guide junior team-members in their execution of Sub block-level layouts & review their work. Contribute to effective project-management. Develop recent flows/methodologies to reduce the stdcells manual effort & increase the productivity