This role is about owning the silicon journey from floorplan to signoff.
- 5–8 years in physical design and SoC implementation
- Strong experience in Cadence tools: Innovus, Tempus, Voltus, Quantus
- Hands-on with floorplanning, PnR, STA, and EM/IR closure
- Proven ability to meet aggressive PPA targets
- Experience in clock tree, routing optimization, and extraction
- Strong understanding of ASIC design flow and signoff
- Exposure to automation and flow improvements
- Solid collaboration and execution mindset
If PPA targets excite you more than scare you, this one’s for you.