Participate in design reviews both internally and potentially with customers to explain design choices and robustness. Work with people across multiple sites including overseas. Help with creating IP EDA views: Behavioral/Verilog-A, timing views, abstract etc. Participate in silicon bring up, characterization, & perform correlations against models & simulations. Prior experience in taking full ownership of at least on of the sub-blocks like PLL, DLL, CDR, high speed receiver with equalization, transmitter front end and high speed data path. Candidate should have deep understanding of analog and mixed signal circuit with experience in high speed link. Candidate must have experience in Serdes/Parallel Interface. Experience with TX RX Equalization (FFE/CTLE/DFE) is must Experience with various CDR and Clocking architecture. Candidate should have experience in finfet 10nm and below. Able to create block level specification based on link budget. Able to create system level modeling using VerilogA/Python.



Should be able to work with Packaging/Board team. Should have knowledge of ESD. Experience in lab testing and work with validation team to analysis data. High speed I/O cell designs such as DDR, LVDS, HSTL, CML. Power Delivery circuits such as Bandgap, LDO, Bias circuits. Solid fundamental knowledge for AMS design, Advanced CMOS and FinFet technologies. Understanding of Mismatch analysis & Monte-Carlo methodology/sims, transistor level Circuit level noise analysis. Supervision of complex and/or sensitive analog layout and defining IP floorplan Experience with industry standard tools such as Cadence ADE, Spectre, AMS verification, EM/IR flows, MATLAB, Calibre etc. Working knowledge of Mixed mode simulation, Signal Integrity and ESD desired. M.S./M.Tech, BS/BE (Electronics) Experience Required : 5+ Years

📌 Design/Senior/staff/Principal Engineer ASIC Analog Design (Bengaluru)
🏢 Recognized
📍 Bengaluru