- 8+ years of industry experience in ASIC verification.
- Experience with large and complex chip designs.
- Knowledge of logic design, state-machines, memory and FIFO designs.
- Proficient in Verilog HDL, PLI.
- Proficient in synthesis tools (Synopsys or Ambit).
- Experience and familiarity with backend tools.
- Experience with timing closure issues for large and complex chips.
- Positive knowledge of networking systems.
- Masters degree in EE or CS from a reputable engineering institution.
- Email your resume to
[email protected] with Job Code – SDE in the subject line.
📌 Senior Design Engineers (Bengaluru)
🏢 Perfectus Technology
📍 Bengaluru