B.Tech / M.Tech with 12 to 18 years of experience exclusively in DFT.
"DFT Architect.
SOC and SS level implemenetation, verification. Post Si debug.
Deploying DFT Flow for implementation, verification, pattern generation, pattern delivery, Si bring-up."
Should be able to handle team of up to 12 members. Drive team towards meeting Milestone in high pressure situation. Should be able to handle multiple clients, projects simultaneously.
Capable of DFX and DFD Feature insertion and verification (Intel and AMD flow)
Must be aware of interface to ATEs, tester hand-off languages/TDL/Verilog and must know to drive/modify test procedures. Desirable to have experience in Post Silicon Debug on Tester.
Should either have hands-on or solid co-working experience with other dependent functions, Constraints development,
STA & Physical Design. It is highly desirable that candidate should be able to come up with an implementation plan independently given a test plan.
Good at Communication. Conversant with Multi-site working culture. Able to guide team remotely.
Should be capable of developing Flow Methodology.
Passionate for Training juniors, skill development, Training plan and co-ordination.