As a Functional Verification Engineer, a typical day involves designing and implementing comprehensive testbenches to ensure the functional accuracy of digital designs at both block and system levels. The role requires creating various types of tests, including constrained-random, directed, and coverage-driven, to thoroughly validate the design. Collaboration with design and architecture teams is essential to identify potential corner cases and guarantee exhaustive functional coverage prior to tape-out. This position demands a proactive approach to problem-solving and continuous communication across multiple teams to maintain high-quality verification standards throughout the project lifecycle.
Roles & Responsibilities:
- Expected to be an SME, collaborate and manage the team to perform.
- Responsible for team decisions.
- Engage with multiple teams and contribute on key decisions.
- Provide solutions to problems for their immediate team and across multiple teams.
- Lead efforts to identify verification gaps and propose creative strategies to enhance test coverage.
- Mentor junior team members to develop their skills and ensure alignment with project goals.
- Coordinate cross-functional reviews to align verification objectives with design specifications.
Professional & Technical Skills:
- Must To Have Skills: Proficiency in SoC Verification.
- Strong knowledge of testbench development methodologies and verification languages such as System Verilog and Universal Verification Methodology.
- Experience in creating and executing constrained-random, directed, and coverage-driven tests to validate complex digital designs.
- Ability to analyze functional coverage metrics and identify coverage holes to improve verification completeness.
- Familiarity with simulation tools and debugging techniques to efficiently isolate and resolve design issues.
- Capability to collaborate effectively with design and architecture teams to understand design intent and verify corner cases.