Job Description
About PQAngels Technologies :
PQAngels Technologies Pvt. Ltd. is a product engineering company delivering end-to-end engineering solutions across the silicon-to-software stack. We partner with semiconductor companies, OEMs, and technology-driven enterprises to accelerate product development through expertise in ASIC/SoC Design, Design Verification, Physical Design, Embedded Systems, Firmware, Software Engineering, AI, Cloud, and Dev Ops.
Role Overview :
We are looking for an experienced Senior Design Verification Engineer with strong expertise in System Verilog, UVM, and ASIC/SoC Functional Verification. The ideal candidate should have hands-on experience in developing reusable verification environments, executing complex verification plans, achieving coverage closure, and collaborating with cross-functional design teams throughout the product development lifecycle.
Key Responsibilities :

- Develop comprehensive verification plans based on architecture and design specifications.

- Design, develop, and maintain reusable UVM-based verification environments.

- Create scalable testbenches and verification components for IP, subsystem, and SoC-level verification.

- Develop directed, constrained-random, and regression test cases.

- Implement System Verilog Assertions (SVA) for protocol and functional verification.

- Drive functional, code, and assertion coverage closure.

- Perform debugging using waveform analysis and root cause analysis techniques.

- Execute regression suites and analyze failures.

- Verify complex protocols such as PCIe, DDR, USB, Ethernet, AXI, AHB, APB, MIPI, CXL, or UCIe.

- Collaborate closely with RTL, DFT, Physical Design, and Architecture teams.





- Participate in design reviews and provide verification feedback.

- Mentor junior verification engineers and review verification deliverables.

- Support verification sign-off activities and project milestones.

- Prepare technical documentation, verification reports, and coverage metrics.

RequirementsProgramming & Verification

- System Verilog

- Universal Verification Methodology (UVM)

- System Verilog Assertions (SVA)

- Functional Coverage

- Constrained Random Verification

- Scoreboards & Functional Checkers

- Register Abstraction Layer (RAL)

Protocol Verification

- PCI Express (PCIe)

- DDR / LPDDR

- AXI

- AHB / APB

- USB

- Ethernet

- MIPI

- CXL

- UCIe

- SPI

- I2C

- UART

EDA Tools

- Synopsys VCS

- Cadence Xcelium

- Siemens Questa Sim

- Verdi

- DVE

Scripting
- Python

- Perl

- TCL

- Shell Scripting

Preferred Qualifications
- Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.

- 4–12 years of experience in ASIC/SoC Design Verification.

- Experience verifying complex IPs, subsystems, or full-chip SoCs.

- Robust understanding of digital design concepts and RTL (Verilog/System Verilog).

- Experience with lint, CDC, RDC, and formal verification is an added advantage.

- Familiarity with Git, Perforce, or other version control systems.

- Experience working in Agile development environments.

Benefits

- Competitive Salary

- Health Insurance

- Performance-Based Incentives

- Learning & Development Opportunities

- Professional Growth & Career Advancement

- Flexible Leave Policy

- Collaborative Work Environment

Requirements
• System Verilog • UVM • SVA • Functional Coverage • Protocol Verification • Python/TCL • VCS • Xcelium • Questa Sim • Verdi

📌 Senior Design Verification Engineer (Bengaluru)
🏢 PQANGELS TECHNOLOGIES
📍 Bengaluru