Key Responsibilities:

- Architecture Design: Develop and optimize PCIe architectures for high-performance SoC designs, including switches, interconnects, and communication protocols.
- Protocol Expertise: Design and implement PCIe solutions that support various communication protocols such as PCIe, CXL and AMBA/AXI.
- System understanding: Understanding of PCIe solutions for overall SoC design, ensuring seamless communication between various IP blocks and subsystems.
- Performance Analysis: Conduct detailed performance analysis and benchmarking of PCie designs to identify bottlenecks and areas for improvement.
- Collaboration: Work closely with hardware, software, and verification engineers to ensure that PCie designs meet system requirements and performance goals.
- Troubleshooting: Identify and resolve complex issues in PCIe design and simulation.
- Research and Development: Stay updated with the latest advancements in PCIe Specifications and contribute to the development of new standards/methodologies and tools. Actively participate in research projects to explore new PCIe Programs and protocols.

Primary Skills

- Proficient in PCIe design and optimization techniques.
- Strong understanding of digital design principles and SoC architecture.
- Experience with hardware description languages (HDLs)



such as Verilog, System-Verilog
- Knowledge of RTL simulation tools and Verification environments (e.g., Cadence, Synopsys, UVM).
- Expertise in various communication protocols such as PCIe, CXL, and Amba/AXI.

Soft Skills

- Excellent problem-solving and analytical skills.
- Strong communication and collaboration abilities.
- Ability to work independently and in a team workplace.
- Attention to detail and a commitment to quality.
- Enthusiasm for research and development.

Preferred Skills:

- Experience with PCIe Gen-4/5/6 protocol skills
- Knowledge of ASIC design flows.
- Familiarity with scripting languages (e.g., Python, Perl).
- Experience with version control systems (e.g., Design-sync, Git).
- Background in PCie design, PCie Architecture and Serdes concepts, low-power design and optimization.
- Synthesis Tools like (DC/DC-NXT) or Fusion compiler
- Synthesis Constraints and Timing Concepts (STA)
- Spyglass (lint, DFT, PM, CLK/RST, CDC/RDC)
- Formal Verification check like Formality or Conformal LEC)
- Publication history in relevant technical journals/IEEE/ conferences is a plus

Skills: Git, Problem Solving, Verilog, Performance Analysis, Python

Experience: 15.00-20.00 Years

📌 VLSI Technical Design and Verification Engineer (Bengaluru)
🏢 VMware
📍 Bengaluru