B.Tech / M.Tech with 8 to 12 years of experience exclusively in DFT.
"Sub-system / SOC level: Hands-on experience to do scan insertion, EDT, LBIST, ATPG coverage improvement, Pattern Generation/Simulation. Should have expertise on Simulation debug No-timing/Timing.
Exposure to SSN insertion is plus."
"Sub-system / SOC level: Hands-on Experience to do MBIST Insertion, Verification, Pattern generation. Thorough with Diagnostics and Repairability concepts.
Valuable to have functional & integration knowledge of TAP controllers and JTAG. Working knowledge of JTAG, iJTAG, ICL, PDL etc."
"Intel and AMD DFX insertion and val at SS and Top level.
QC checks post RTL insertion, SpyGlass, CDC, RDC, VCLP etc."
Should be able to handle team of 4-6 members. Drive team towards meeting Milestone in high pressure situation.
Good to have functional & integration knowledge of TAP controllers and JTAG
Must be aware of interface to ATEs,
tester hand-off languages/TDL/Verilog and must know to drive/modify test procedures. Desirable to have experience in Post Silicon Debug on Tester.
Should either have hands-on or strong co-working experience with other dependent functions, Constraints development, STA & Physical Design. It is highly desirable that candidate should be able to come up with an implementation plan independently given a test plan.
Good at Communication. Conversant with Multi-site working culture. Able to guide team remotely.
Have done Technical front ending with client earlier.