Memory Layout Design Engineer (India)

Memory Layout Design Engineer (India)

06 Aug
|
Mirafra Software Technologies
|
India

06 Aug

Mirafra Software Technologies

India

Memory Layout Design Engineer

Location: Bangalore

Job Description:

- Development of key building blocks of memory architecture such as Row Decoder, IO, Control.
- Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing.
- Knowledge of EM/IR requirements. Compiler level integration, verification of Compiler/Custom memories.
- Should possess valuable knowledge on CMOS fabrication process, foundries and challenges in latest technology nodes

Experience (years) : 3-6 years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

📌 Memory Layout Design Engineer (India)
🏢 Mirafra Software Technologies
📍 India

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