Senior Test Lead - Design Validation

Experience: Not Available to Not Available years

Location: Bangalore, India

Skills: ASIC verification, SoC verification, SV, UVM, verification flows, constrained random verification, functional coverage, assertion methodology, Ethernet, MAC, PCS, TCP/IP, Forwarding, Lookups, High bandwidth datapath, Queuing Algorithms, Dequeuing Algorithms

Job Summary
As part of the verification team, will be responsible for independently developing and maintaining leading-edge constrained-random verification environments and using them to drive functional correctness of innovative designs

Key Responsibilities
developing and maintaining leading-edge constrained-random verification environments

Skill Requirements




experience in ASIC/SoC verification with SV/UVM environments
• In-depth knowledge of verification flows
• Explicit understanding of constrained random verification process, functional coverage, assertion methodology & philosophy
• Team player with excellent communication skills and the desire to take on diverse challenges
• Prior verification experience in one or more of the following domains is must:
• Ethernet; MAC/PCS; TCP/IP; Forwarding/Lookups
• High bandwidth datapath; Queuing/Dequeuing Algorithms

Other Requirements
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📌 Senior Test Lead Design Validation (Bengaluru)
🏢 HCL Technologies
📍 Bengaluru