Job Summary
8+ years experience DV engineer responsible for overseeing multiple design teams and establishing organizational design standards.
Key Responsibilities
• Development and maintenance of UVM testbenches, including agents, sequences, scoreboards, monitors, and checkers
• Test planning, execution, and closure at IP level
• Writing and debugging constraint-random tests
• Development and analysis of functional coverage and code coverage
Skill Requirements
• ASIC IP-level verification using SystemVerilog and UVM
• Development and maintenance of UVM testbenches, including agents, sequences, scoreboards, monitors, and checkers
• Robust Debugging Skills
Other Requirements
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