Senior RTL Design Lead

Experience: Not Available to Not Available years

Location: Bangalore, India

Skills: Verilog, VHDL, FPGA, ASIC, SoC, Modelsim, Synopsys Design Compiler, UVM, SystemVerilog

Job Summary
Experience working with Synopsys HAPS (High‑Performance ASIC Prototyping System) Proficient in logical partitioning of large designs for FPGA prototyping Hands-on experience mapping large ASIC/SoC RTL designs across multiple FPGAs Ability to validate and debug the complete SoC functionality on FPGA platforms

Key Responsibilities
1. Utilize Advanced RTL Design Techniques And Tools, Such As Verilog And VHDL, To Create Efficient And Optimized Hardware Designs That Align With User Requirements And Business Goals.
2. Lead And Mentor A Team Of RTL Designers, Providing Technical Guidance And Ensuring The Successful Delivery Of High-Quality Design Solutions That Adhere To Project Timelines And Specifications.
3. Present And Articulate Design Concepts, Strategies,



And Solutions To Stakeholders, Playing A Pivotal Role In Shaping The Overall Design Vision And Ensuring Alignment With Organizational Objectives.
4. Conduct Regular Reviews Of Design Processes And Methodologies, Integrating Industry Trends And Emerging Technologies To Drive Innovation And Enhance Design Excellence.

Skill Requirements
1. Advanced Proficiency In RTL Design Using Verilog And VHDL.
2. Solid Knowledge Of Digital Design Principles And Methodologies.
3. Familiarity With Simulation Tools Such As Modelsim And Synthesis Tools Like Synopsys Design Compiler.
4. Robust Understanding Of Design Verification Processes And Tools, Including UVM And SystemVerilog.

Other Requirements
1. Certification In RTL Design Or Equivalent (Optional But Valuable).

📌 Senior RTL Design Lead (Bengaluru)
🏢 HCL Technologies
📍 Bengaluru