As a Sr Principal Verification Engineer at Cadence, you will play a crucial role in revolutionizing the semiconductor design industry by leveraging artificial intelligence to redefine the verification landscape. You will collaborate with a highly skilled team of machine learning engineers and software engineers to architect, design, and validate the next generation of verification methodologies. Here is a breakdown of your role:Key Responsibilities:- Contribute to the application of machine learning techniques to streamline traditional pre-silicon functional verification methodologies like formal verification and UVM.- Develop agentic AI solutions using LLMs and the latest ML technologies to accelerate pre-silicon Design Verification process.- Utilize AI-enhanced Electronic Design Automation (EDA) tools to improve and expedite both the design and verification lifecycles.- Engage with customers to understand requirements and deliver innovative verification strategies.- Collaborate effectively with machine learning and software engineering teams to validate output correctness, efficiency, and quality.- Stay updated on advancements in AI-powered hardware verification and actively participate in fostering internal knowledge growth.Qualifications Required:- Bachelors or masters degree in electrical engineering, Computer Engineering, or related field.- More than 12-15 years of proven expertise in at least one pre-silicon ASIC verification methodology such as Formal, SV/UVM, and/or OVM.- Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools.- Hands-on experience with industry-standard EDA tools (e.g., Jasper, Xcelium, IMC).- Strong programming skills in Verilog, System Verilog,



and Python.- Excellent communication skills and the ability to thrive in a team-oriented environment.- Self-motivated with a proactive approach to problem-solving, continuous learning, and innovation.- Exposure to LLMs and ML technologies like RAG, RFT, RL, and Agentic frameworks would be a plus.In addition to contributing to cutting-edge technology, at Cadence, you will benefit from employee-friendly policies focusing on your physical and mental well-being, career development, learning opportunities, and recognition of your success. The unique One Cadence One Team culture promotes collaboration and ensures customer success. You will have access to multiple avenues of learning and development tailored to your interests. Join a diverse team of passionate individuals dedicated to making a difference in the world of technology every day. As a Sr Principal Verification Engineer at Cadence, you will play a crucial role in revolutionizing the semiconductor design industry by leveraging artificial intelligence to redefine the verification landscape. You will collaborate with a highly skilled team of machine learning engineers and software engineers to architect, design, and validate the next generation of verification methodologies.



Here is a breakdown of your role:Key Responsibilities:- Contribute to the application of machine learning techniques to streamline traditional pre-silicon functional verification methodologies like formal verification and UVM.- Develop agentic AI solutions using LLMs and the latest ML technologies to accelerate pre-silicon Design Verification process.- Utilize AI-enhanced Electronic Design Automation (EDA) tools to improve and expedite both the design and verification lifecycles.- Engage with customers to understand requirements and deliver creative verification strategies.- Collaborate effectively with machine learning and software engineering teams to validate output correctness, efficiency, and quality.- Stay updated on advancements in AI-powered hardware verification and actively participate in fostering internal knowledge growth.Qualifications Required:- Bachelors or masters degree in electrical engineering, Computer Engineering, or related field.- More than 12-15 years of proven expertise in at least one pre-silicon ASIC verification methodology such as Formal, SV/UVM, and/or OVM.- Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools.- Hands-on experience with industry-standard EDA tools (e.g., Jasper, Xcelium, IMC).- Strong programming skills in Verilog, System Verilog, and Python.- Excellent communication skills and the ability to thrive in a team-oriented environment.- Self-motivated with a proactive approach to problem-solving, continuous learning, and innovation.- Exposure to LLMs and ML technologies like RAG, RFT, RL, and Agentic frameworks would be a plus.In addition to contributing to cutting-edge technology, at Cadence, you will benefit from employee-friendly policies focusing on your physical and mental well-being, career development, learning opportunities, and recognition of your success. The unique One Cadence One Team cultu

📌 Sr Principal Verification Engineer (Noida)
🏢 Cadence Design Systems
📍 Noida