As a Senior Engineer in ASIC Design Verification at eInfochips, you will play a crucial role in developing UVM-based SV test-benches, defining test plans for block, sub-system, and SOC levels, and working with various subsystems such as PCIe, UCIe, NVMe, NAND, DDR, and CPU. Your deep understanding of verification methodologies, flows, and quality metrics will be essential for the successful execution of verification projects. You will be responsible for mentoring junior engineers, client communication, technical reviews, and overall project management.**Key Responsibilities:**- Develop UVM-based SV test-benches- Define block, sub-system, and SOC top level test plans- Work with PCIe, UCIe, NVMe, NAND, DDR, and CPU subsystems- Conduct in-depth technical reviews- Mentor junior engineers- Communicate with clients- Track technical and management aspects of projects**Qualifications Required:**- Minimum 4 years of experience in System Verilog HVL- Minimum 3 years of experience in OVM/UVM/VMM/Test Harness- Proficiency in developing assertion, checkers, coverage, and scenarios- Experience in executing at least 1 SoC Verification project- Ability to develop test and coverage plans, verification environments, and validation plans- Knowledge of industry standard protocols like Ethernet, PCIe, MIPI, USB, or similarIf you are interested in this role and meet the qualifications, please share your CV to the email address provided. Feel free to share this chance with your network of friends who are seeking job opportunities.



As a Senior Engineer in ASIC Design Verification at eInfochips, you will play a crucial role in developing UVM-based SV test-benches, defining test plans for block, sub-system, and SOC levels, and working with various subsystems such as PCIe, UCIe, NVMe, NAND, DDR, and CPU. Your deep understanding of verification methodologies, flows, and quality metrics will be essential for the successful execution of verification projects. You will be responsible for mentoring junior engineers, client communication, technical reviews, and overall project management.**Key Responsibilities:**- Develop UVM-based SV test-benches- Define block, sub-system, and SOC top level test plans- Work with PCIe, UCIe, NVMe, NAND, DDR, and CPU subsystems- Conduct in-depth technical reviews- Mentor junior engineers- Communicate with clients- Track technical and management aspects of projects**Qualifications Required:**- Minimum 4 years of experience in System Verilog HVL- Minimum 3 years of experience in OVM/UVM/VMM/Test Harness- Proficiency in developing assertion, checkers, coverage, and scenarios- Experience in executing at least 1 SoC Verification project- Ability to develop test and coverage plans, verification environments, and validation plans- Knowledge of industry standard protocols like Ethernet, PCIe, MIPI, USB, or similarIf you are interested in this role and meet the qualifications, please share your CV to the email address provided. Feel free to share this opportunity with your network of friends who are seeking job opportunities.

📌 Senior Engineer - ASIC Verification (Pune)
🏢 Important Company of the Sector
📍 Pune