Junior Digital Verification

Experience: Not Available to Not Available years

Location: Catania

Skills: Verilog, SystemVerilog, UVM, Python, Perl

Your Responsibilities
Develop and implement testbenches and verification environments for digital IP blocks and sub-systems.
• Create and execute test plans, test cases, and functional coverage models.
• Debug design issues and work closely with design engineers to achieve functional correctness.
• Analyze verification results and generate coverage reports to ensure thorough testing.
• Participate in verification methodology development and contribute to continuous improvement efforts.
• Collaborate with cross-functional teams including design, architecture, and software.
• Document verification processes, results, and findings clearly and concisely.





Your Profile
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Basic understanding of digital design concepts and HDL languages (Verilog/SystemVerilog).
• Familiarity with UVM methodology is a plus.
• Knowledge of scripting languages (e.g., Python, Perl) is desirable.
• Strong analytical and problem-solving skills with attention to detail.
• Excellent communication and teamwork skills.
• Proactive attitude and eagerness to learn and develop in a rapid-paced environment.

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