This is an opportunity to join a top-notch Power Management IC Team with Renesas leading Automotive Business Unit. You will be part of a very skilled group of engineers who are helping build world-class automotive PMIC products that will power tomorrow’s automobiles. You will design complex chips that includes various analog and digital control circuitry and work very closely with all aspects of chip design – from writing specifications to developing tests for mass production. You will be a key contributor to the digital DFT design team and work closely with the digital design team for meeting TEST requirements for Automobile and work closely with test engineering teams for validating the test patterns and meeting ASIL-B/D requirements. You will have an opportunity to work on recent designs, insert Lbist and shape the company’s pathway for success. Your responsibilities, depending on your level of experience and skill level, will be a mix of the following:
- Inserting DFT/Scan on digital logic, ATPG, validating test patterns on pre and post layout gate level netlist.
- Delivering test patterns to TEST engineering team and validating them on silicon.
- Inserting Logicbist with industry standard tools.
- Improving scan coverage and modifying RTL for scan.
- Reduce test time.
- Exposure to automotive test requirements, ASIL, is highly preferred.
- Participate in all aspects of design flow - Micro-architecture, Design partitioning, RTL Verilog / System Verilog Design, DFT, Generating Timing Constraints, Synthesis, Interaction with P&R; Team, Timing Analysis, LINT, CDC.
- Working closely with Architects, Design, P&R;, Test, Silicon validation teams.
- Assisting with top level test-bench creation for scan and running gate level simulations.
- Developing detailed design documents and help writing DFT specification, documents and collateral.
- Holding and participating in key design reviews and completion of various checklists.