We are looking for an experienced Physical Design (PD) Solution Architect to lead physical implementation strategy, methodology definition, PPA optimization, and implementation planning for complex SoCs. The ideal candidate will serve as the technical authority for physical design architecture, feasibility analysis, and successful project delivery across global teams.
Requirements
Mandatory Skills
experience in Physical Design.
Multiple successful tape-outs on advanced technology nodes (10nm and below).
Solid expertise in
Floorplanning
CTS (Clock Tree Synthesis)
Timing Closure
Power Optimization
Hands-on experience with:
Synopsys ICC2
Fusion Compiler
Cadence Innovus
Experience with UPF and multi-voltage designs.
Experience working on large SoCs (>100M gates).
Solid understanding of signoff methodologies.
Mandatory experience with TSMC technology nodes.
Experience with AI-based EDA tools such as DSO or Cerberus.
Experience with HBM/HMC memory systems.