Work on creating verification plan for RISC-V based application specific IP
Build Standalone IP test bench using System Verilog
Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC)
Use the IP/SOC RTL in system verilog based logic verification setting complete the functional verification
Generate functional and code coverage metrics, collaborate with IP developers on the correctness completeness of IP functionality.
Deliver the functional test vectors needed to be used for post-silicon validation.
Be the single point contact for the concerned IP Verification and enable the Tapeout for all control ASICs of Enphase
Who you are and what you bring
Proficient in UVM, Verilog, SystemVerilog, C, Python. Working on the HW/SW interface.
Solid understanding and experience of logic verification environment (UVM System Verilog)
Robust understanding of RISC-V architecture functional verification
Experience with processor toolchains (compiler, assembler, simulator).
Experience with processor verification. Directed tests and random program generated tests.
Experience with functional processor simulators.
Experience with verification of secure processor boot code.
Experience with Floating point instructions implementation verification in micro controller based ASIC designs
Ability to quickly adapt to other categories of C-based/System Verilog based IP verification
Experience and ability to bring complex SOCs into the physical world and into production.
Excellent problem solving skills, written verbal communication skills
Logic Verification #Embedded C Verification #ARM #Boot.
Prior hands on work experience of at least 8 years in Logic IP Verification based on System Verilog.