Soc Dft Engineer Bengaluru

Soc Dft Engineer Bengaluru

05 Aug
|
ACL Digital
|
Bengaluru

05 Aug

ACL Digital

Bengaluru

SoC DFT Engineer

:
Scan insertion.
SCAN DRC/Coverage debug.
ATPG Pattern generation.
Gate level simulations ( Zero delay/Timing Delay simulations).
Worked on JTAG/P1500 protocols.
Perl/Tcl scripting.
Timing/Formal verification/PD flow knowledge is plus.

Location: Bangalore

Notice Period: Immediate

Experience: 5+ Years

📌 Soc Dft Engineer Bengaluru
🏢 ACL Digital
📍 Bengaluru

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