Job Description:

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet rigorous criteria for achieving Right-First-Time silicon. Candidates must have extensive experience in block-level and top-level layout activities, including floor-planning, partitioning, placement, clock tree synthesis, routing, and physical verification.

Responsibilities include, but are not limited to:
Understanding SoC for top-down/bottom-up physical design integration in 5nm and lower technologies.
Demonstrating deep functional knowledge of P&R; flows, with the ability to quickly adapt to internal methodologies.
Implementing timing and functional ECOs.
Executing P&R;, extraction, physical verification, and working toward STA closure.
Building recent automation flows as needed and adapting existing flows for re-use.
Maintaining proficiency in Cadence/Synopsys/Mentor EDA tools for P&R;, PV, STA, and ECO.




Developing automation with high expertise in industry-standard programming languages.
Clearly understanding execution requisites and leading by example.
Driving tangible improvements in turnaround time (TAT) alongside better quality.

Minimum Qualifications:
MSEE/MSCS with 6+ years of experience, or BSEE/BSCS with 8+ years of experience.
Deep understanding of backend digital design flows.
Proficiency in timing and physical constraints.
Proficiency in handling EDA tools across floorplan, partition, placement, CTS, and route stages for SoC TOP.
Proficiency with backend EDA tools such as Genus, Innovus, Quantus, Tempus, DC, Star-RCXT, PT, PrimeRail, Voltus, Redhawk.
Proficiency in Tcl and Perl.
Excellent analytical skills.
Proven ability to collaborate in a multi-functional workplace across different sites and time zones.

R026380

📌 Senior Engineer Pune
🏢 Broadcom
📍 Pune