Job Summary
Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM)
Design and write robust verification environments (testbenches) to achieve high code coverage
Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality
Debug and analyze verification failures to identify the root cause of design issues
Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements
Participate in code reviews and ensure adherence to verification coding standards
Stay up-to-date with the latest verification tools and methodologies

Qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)
5-7 years of experience in design verification for ASICs or SoCs




Strong understanding of digital design principles (combinational logic, sequential logic)
Proven ability to develop and debug complex verification environments
Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM)
Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus
Excellent analytical and problem-solving skills
Solid communication and collaboration skills to work effectively in a team environment

Benefits:
Competitive salary and benefits package
Opportunity to work on leading-edge technologies and projects
Collaborative and dynamic work environment
Potential for professional development and career advancement

📌 Design Verification Engineer (Chennai)
🏢 HCLTech
📍 Chennai