Digital Design Engineer

Experience: Not Available to Not Available years

Location: Pune

Skills: Verilog, SystemVerilog, ASIC front-end design flows, C, C++, design verification techniques, test bench development, UVM, System-Verilog assertions, checkers, Unified Power Format, Perl, Python

Duties and Responsibilities
The Digital Design Engineer is responsible for defining and realizing Digital functions on IPs, Subsystem or IC level based on required specifications. He is responsible for design, verification and evaluation of those. He is accountable for designing according to specifications, quality and reliability needs. Participation in problem solving for Digital and system domain of the device. Author of the design-specific documentation for internal and external use. The candidate will work as a design engineer for wireless/communication ASICs development. The main responsibilities include IP delivery and silicon validation support.



The candidate may be working full ASIC design cycle from design, RTL coding, verification, synthesis, timing closure, DFT, backend support and silicon bring-up.

Core Responsibilities and Accountabilities:
• Strong Verilog/SystemVerilog coding skills.
• Working knowledge of ASIC front-end design flows.
• Working knowledge of C/C++.
• Working experience of design verification techniques and test bench development.
• Strongly desired: Working knowledge of UVM is a desirable.
• Good knowledge of System-Verilog assertions, checkers and other design verification techniques are a plus.
• Working experience of Unified Power Format for simulation, synthesis and CLP checking is a plus.
• Positive knowledge of scripting languages. Perl and Python are plusses.

Roles and Responsibilities
More information about NXP in India... #LI-2734

📌 Digital Design Engineer (Pune)
🏢 NXP Semiconductors
📍 Pune