Senior Principal Design Verification (DV) Engineer

Experience: 12+ years of hands-on expertise

Location: Pune, India

Skills: ARM-based microcontrollers, low-power design verification, verification strategy, verification methodology, verification coverage goals, design verification closure, UVM-based verification environments, RTL simulations, netlist simulations, SystemVerilog, constrained-random verification methodologies, Synopsys VCS, Cadence Xcelium, Mentor Graphics Questa, low-power verification using UPF, gate-level simulations, power-aware simulations, SystemVerilog Assertions (SVA), functional coverage, SPI, I²C, UART, USB, PCIe, Ethernet, eSPI, Flash memory, security IPs, crypto engines, Analog IPs, ADC, DAC, PLLs

Role Overview
We are seeking a highly experienced Senior Principal Design Verification (DV) Engineer with 12+ years of hands-on expertise to lead verification strategy and execution for complex System-on-Chip (SoC) designs. The ideal candidate will possess deep technical knowledge of ARM-based microcontrollers, low‑power design verification, and extensive experience verifying multiple interfaces and security IPs. This is a senior, hands-on technical leadership role requiring strong collaboration, mentorship, and the ability to drive verification closure in a fast-paced environment.

Key Responsibilities

Verification Strategy & Leadership
Define and own SoC-level and IP-level verification strategy, methodology, and coverage goals.
Drive design verification (DV) closure across diverse IPs and subsystems, ensuring maximum quality and coverage.
Ensure compliance with functional safety and security requirements.
Guide the team in developing and improving verification flows for maximum reuse and efficiency.




Mentor junior and senior DV engineers while closely collaborating with design teams for issue resolution and sign-off.

Hands-On Verification Execution
Execute verification plans aligned with product specifications and architectural requirements.
Develop, debug, and run UVM-based verification environments for RTL and netlist simulations.
Create and maintain test cases, stimulus, and assertions within the chosen verification framework.
Run simulations and debug test cases across multiple design models: RTL, Power-aware RTL, Gate-level, FPGA prototypes, Emulation platforms.
Perform regression runs and analyze code and functional coverage to ensure verification completeness.
Work effectively in both SoC-level and IP-level verification environments.

Required Qualifications
Experience
12+ years of experience in SoC/IP design verification.
Proven track record of successful tape-outs of multiple SoCs.
Technical Skills
Solid expertise in ARM-based microcontrollers and SoC-level verification.
Proficiency in SystemVerilog, UVM, and constrained-random verification methodologies.
Hands-on experience with industry-standard EDA tools: Synopsys VCS, Cadence Xcelium, Mentor Graphics Questa.
Experience with low-power verification using UPF.
Exposure to gate-level simulations and power-aware simulations.
Strong knowledge of SystemVerilog Assertions (SVA) and functional coverage.
Verification experience with standard interfaces, including: SPI, I²C, UART, USB, PCIe, Ethernet, eSPI.
Knowledge of Flash memory and security IPs (crypto engines and security subsystems) is a plus.
Familiarity with common Analog IPs used in microcontroller designs: ADC, DAC, PLLs.
Soft Skills
Comfortable working in a fast-paced, dynamic environment.
Strong team player with excellent communication and collaboration skills.
Ability to mentor team members and influence cross-functional stakeholders.
More information about NXP in India... #LI-2734

📌 Senior Principal Design Verification (DV) Engineer (Pune)
🏢 NXP Semiconductors
📍 Pune