Job Summary
Valuable understanding of ASIC/SoC life cycle. Has participated in multiple ASIC/SoC verification till tapeout stage. Experience writing ASIC/SoC testplans.
Key Responsibilities
• To design and architect large-scale solutions, ensuring scalability, performance, and security.
• To train and develop team so as to ensure that there is an adequate supply of trained manpower in the said technology and delivery risks are mitigated.
• To continuously upskill with cutting-edge tech to deliver high-quality, future-proof solutions meeting client expectations and industry standards.
• To leverage domain/tech expertise to gather client needs, deliver solutions, and craft a technology strategy aligned with business goals.
Job Description
Good understanding of ASIC/SoC life cycle. Has participated in multiple ASIC/SoC verification till tapeout stage. Experience writing ASIC/SoC testplans.
1. Experience in ASIC/SoC Testbench definition.
2.
Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM).
1. Expertise & hands-on experience in OVM/UVM methodologies using SV.
2. Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.
1. Experience in developing TB components for SOC with C, SV.
1. Experience in developing TB components, including functional coverage implementation and assertion coding.
2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.
3. Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.
4. Experience in SOC C based tests coding & debugging.
Experience in Gate level simulation & netlist debugging.
Experience in regression failure analysis.
Functional and Code Coverage closure.
Experience in Utilizing scripting languages like Perl/Shell scripting to automate regression tests and parse large simulations.