Senior Designer - Design Validation

Experience: Not Available to Not Available years

Location: Bengaluru, India

Skills: SystemVerilog, UVM, Verification methodologies, Debugging, Functional coverage, Assertions (SVA), Simulation tools: VCS, Xcelium, Questa, Scripting: Python, Perl, Shell, TCL, Formal verification, Protocol verification (PCIe, USB, AXI, DDR), Emulation, FPGA validation exposure

Job Summary
DV Engineers verify functionality and correctness of RTL designs using simulation-based and formal verification methodologies.

Key Responsibilities
Develop test plans and verification strategies
Build UVM/SystemVerilog testbenches
Create directed and constrained-random test cases
Perform functional coverage analysis
Debug RTL and simulation failures
Run regressions and ensure verification closure
Work closely with RTL and architecture teams

Skill Requirements
SystemVerilog and UVM
Verification methodologies and debugging
Functional coverage and assertions (SVA)
Simulation tools: VCS, Xcelium, Questa

Other Requirements
Formal verification
Protocol verification (PCIe, USB, AXI, DDR)
Emulation/FPGA validation exposure

📌 Senior Designer Design Validation (Bengaluru)
🏢 HCL Technologies
📍 Bengaluru