Senior Technical Architect - AMS Verification

Experience: Not Available to Not Available years

Location: Bangalore, India

Skills: AMS Verification methodologies, Cadence Virtuoso, Synopsys VCS, Mentor Questa, SystemVerilog, UVM, Verilog-AMS, VHDL-AMS, analog behavioral modeling, mixed-signal simulation, assertion-based verification, analog IC design principles, device physics, circuit analysis, system-level integration, verification coverage strategies, debugging

Job Summary
This role drives the end-to-end architecture and technical leadership of complex AMS Verification solutions, ensuring alignment with business strategies and best practices in analog and mixed-signal design and verification. The position defines the technical vision, mentors the team, and leverages deep domain expertise to deliver robust, scalable, and high-performance verification frameworks that meet client and industry standards.

Key Responsibilities
1. Architect comprehensive verification strategies using AMS Verification methodologies and tools such as Cadence Virtuoso, Synopsys VCS, and Mentor Questa, ensuring scalability, performance, and security across large analog/mixed-signal projects.
2. Design and implement advanced verification environments and testbenches with SystemVerilog and UVM, integrating mixed-signal modeling for robust validation of complex IC designs.
3. Mentor and develop the technical team by providing expert guidance on AMS Verification flows, best practices, and tool usage, ensuring the team’s proficiency in latest verification technologies.




4. Collaborate with business stakeholders to capture requirements and translate them into efficient AMS verification solutions, aligning technical strategy with client objectives.
5. Evaluate and integrate emerging verification technologies, methodologies, and EDA tools to continuously enhance solution quality and future-proof design flows.
6. Define and enforce verification standards, coverage metrics, and quality criteria to ensure regulatory and industry compliance throughout the verification lifecycle.

Skill Requirements
1. Expert knowledge of AMS Verification methodologies, including mixed-signal simulation, assertion-based verification, and analog behavioral modeling.
2. Advanced proficiency in EDA tools such as Cadence Virtuoso, Synopsys VCS, Mentor Questa, and related verification platforms.
3. Excellent skills in SystemVerilog, UVM, and analog behavioral modeling languages (e.g., Verilog-AMS, VHDL-AMS).
4. Strong understanding of analog and mixed-signal IC design principles, including device physics, circuit analysis, and system-level integration.
5. Expert ability to define and implement verification coverage strategies, test planning, and debugging of complex mixed-signal designs.
6. Excellent communication and leadership skills for technical mentoring and stakeholder engagement.

Other Requirements
1. Recommended certifications: Certified Cadence AMS Verification Skilled, Synopsys Certified Verification Specialist (optional but valuable).

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