Verification of Analog and mixed signal circuits. Generation of a Full chip mixed signal simulation environment where analog, digital and FW co-exist. Schematic/behavioral model generation of certain blocks to make FC simulation feasible/productive Device level electrical rule checks - SOA, snapback, sfb etc Static and dynamic simulations to identify the leakage paths SPF extraction and fanout, coupling checks Power cycling simulations - PL and Brown out events Chip level user mode simulations correlating analog subsystems, logic and FW algorithms Design data sheet review and generation of verification plan You will also work and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products to optimize all manufacturing functions and assure the best cost, quality,



root-cause analysis, reliability, time-to-market, and customer satisfaction. Understanding of MOS device physics mainly second order effects Basic knowledge of few analog circuits - CM, BGR, op-amp, regulators, ADC, DAC and charge pumps Familiarity with shell, Perl/python scripts Familiarity with virtuoso, hspice, xa and cosim Familiarity with HDLs - Verilog/SV and Verilog A/AMS Debug enthusiast with system level outlook Ability to grab complex workflows and constant drive to innovate Proven ability to leverage AI‑assisted (vibe) coding techniques to improve efficiency or automate design and analysis methodologies

📌 Staff/Principal AMS Verification Engineer (Hyderabad)
🏢 Important Group
📍 Hyderabad